; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s

define i32 @f(i32 %x) {
; CHECK-LABEL: f:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  ! %bb.0: ! %entry
; CHECK-NEXT:    sub %g0, %o0, %o1
; CHECK-NEXT:    and %o0, %o1, %o1
; CHECK-NEXT:    sethi 122669, %o2
; CHECK-NEXT:    or %o2, 305, %o2
; CHECK-NEXT:    smul %o1, %o2, %o1
; CHECK-NEXT:    srl %o1, 27, %o1
; CHECK-NEXT:    sethi %hi(.LCPI0_0), %o2
; CHECK-NEXT:    add %o2, %lo(.LCPI0_0), %o2
; CHECK-NEXT:    ldub [%o2+%o1], %o1
; CHECK-NEXT:    cmp %o0, 0
; CHECK-NEXT:    move %icc, 0, %o1
; CHECK-NEXT:    retl
; CHECK-NEXT:    mov %o1, %o0
entry:
  %0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
  %1 = icmp eq i32 %x, 0
  %2 = select i1 %1, i32 0, i32 %0
  %3 = trunc i32 %2 to i8
  %conv = zext i8 %3 to i32
  ret i32 %conv
}

define i64 @g(i64 %x) {
; CHECK-LABEL: g:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  ! %bb.0: ! %entry
; CHECK-NEXT:    sub %g0, %o1, %o2
; CHECK-NEXT:    and %o1, %o2, %o2
; CHECK-NEXT:    sethi 122669, %o3
; CHECK-NEXT:    or %o3, 305, %o3
; CHECK-NEXT:    smul %o2, %o3, %o2
; CHECK-NEXT:    sethi %hi(.LCPI1_0), %o4
; CHECK-NEXT:    add %o4, %lo(.LCPI1_0), %o4
; CHECK-NEXT:    sub %g0, %o0, %o5
; CHECK-NEXT:    and %o0, %o5, %o5
; CHECK-NEXT:    smul %o5, %o3, %o3
; CHECK-NEXT:    srl %o3, 27, %o3
; CHECK-NEXT:    ldub [%o4+%o3], %o3
; CHECK-NEXT:    srl %o2, 27, %o2
; CHECK-NEXT:    ldub [%o4+%o2], %o4
; CHECK-NEXT:    add %o3, 32, %o2
; CHECK-NEXT:    cmp %o1, 0
; CHECK-NEXT:    movne %icc, %o4, %o2
; CHECK-NEXT:    or %o1, %o0, %o0
; CHECK-NEXT:    cmp %o0, 0
; CHECK-NEXT:    move %icc, 0, %o2
; CHECK-NEXT:    mov %g0, %o0
; CHECK-NEXT:    retl
; CHECK-NEXT:    mov %o2, %o1
entry:
  %0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
  %1 = icmp eq i64 %x, 0
  %2 = select i1 %1, i64 0, i64 %0
  %3 = trunc i64 %2 to i32
  %conv = zext i32 %3 to i64
  ret i64 %conv
}

; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
declare i32 @llvm.cttz.i32(i32, i1 immarg) #0
declare i64 @llvm.cttz.i64(i64, i1 immarg) #0

attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
